High-Speed Board-to-Board Connector Design Guide
High-Speed Board-to-Board Connector Design Guide
A connector does not become “high-speed” because it has fine pitch. High-speed performance comes from a controlled contact/ground architecture, a repeatable PCB launch and measured channel data.
The correct selection process starts with the interface and channel budget, then evaluates the connector’s S-parameters, pin map, stack height and breakout geometry.
Short answer: Select the connector from loss, reflection and crosstalk data for the exact mated configuration. Simulate it inside the complete channel and validate the assembled boards. An advertised maximum data rate is only a screening claim.
Protocol reference
| Interface | Nominal signaling rate | Common differential target | Design note |
|---|---|---|---|
| SATA 6 Gb/s | 6.0 Gb/s | 100 Ω | One transmit and one receive differential pair |
| PCIe 3.0 | 8.0 GT/s per lane | 85 Ω | Channel requirements depend on topology |
| PCIe 4.0 | 16.0 GT/s per lane | 85 Ω | Connector launch and via stubs become more critical |
| PCIe 5.0 | 32.0 GT/s per lane | 85 Ω | Equalization and channel-budget discipline are essential |
| PCIe 6.x | 64.0 GT/s per lane | 85 Ω | PAM4 signaling; requires generation-specific analysis |
| USB 3.x/USB4 | Generation-dependent | Typically 85–90 Ω family-specific | Use the applicable USB specification |
| Ethernet SerDes | Lane architecture-dependent | Often 100 Ω | Do not equate SerDes lanes with 10GBASE-T cabling |
Values are protocol-level starting points. Use the applicable specification and silicon/channel guidance for final limits.
1. The connector is part of a channel
A typical board-to-board link includes:
- Transmitter package and breakout
- Main PCB traces and vias
- Connector launch
- Connector contacts and ground structure
- Daughter-card launch and routing
- Receiver package
Each element contributes loss, reflection, skew and crosstalk. A connector that performs well in a vendor fixture can underperform if the customer footprint creates long via stubs or breaks the return path.
2. Read the S-parameter package
For serious high-speed selection, request Touchstone files and documentation for the exact connector configuration.
| Data | What it reveals |
|---|---|
| Differential insertion loss | Signal attenuation through the interconnect |
| Differential return loss | Reflections caused by discontinuities |
| Near/far-end crosstalk | Coupling into adjacent channels |
| Mode conversion | Differential-to-common-mode energy |
| TDR/TDT plots | Location and size of impedance discontinuities |
| Victim/aggressor pin map | Which channels were measured together |
Check the reference planes, fixture removal and tested mated height. Comparing two plots with different de-embedding boundaries can be misleading.
3. Impedance is a geometry problem
The connector’s effective impedance depends on:
- Signal-contact shape and separation
- Distance to adjacent grounds/shields
- Housing dielectric properties
- Mated overlap
- PCB pad and anti-pad geometry
- Via field and layer transition
Do not route a nominal 85 Ω PCB pair directly into a footprint without considering the pad capacitance and return-current path. Many suppliers provide optimized launch geometry; treat it as part of the characterized solution.
4. Pin-map strategy
High-speed connectors often need ground contacts around differential pairs. A good pin map:
- Maintains a nearby return path through the mate
- Reduces coupling between adjacent lanes
- Keeps pair members geometrically similar
- Avoids routing high-current switching rails beside sensitive lanes
- Allocates additional grounds near the connector edges
- Supports practical breakout on both PCBs
The lowest-crosstalk map is not always the highest-density map. Model at least the nearest aggressors active.
5. Insertion loss and return loss
Avoid universal connector-only limits such as “less than 1 dB at Nyquist” without reference to a specific interface and channel allocation. The acceptable connector contribution depends on:
- Total channel reach
- PCB material and trace loss
- Number of connectors
- Package loss
- Transmitter equalization
- Receiver equalization
- Compliance topology
Allocate a connector budget at the system level, then confirm that the measured connector plus launch fits it with margin.
6. Crosstalk and mode conversion
Crosstalk increases when pairs share long parallel fields, grounds are sparse, or return currents are forced around gaps. Mode conversion increases when the two sides of a differential pair see different geometry.
Practical controls include:
- Symmetrical breakout
- Ground contacts or shields between channels
- Continuous reference planes
- Matched via structures
- Similar anti-pad geometry for both pair members
- Avoiding voids and split planes beneath the launch
Pair-to-pair spacing rules expressed only as a multiple of trace width are a starting heuristic, not a substitute for field solving or channel simulation.
7. PCB breakout and via design
At higher generations, the connector footprint can dominate the local discontinuity. Review:
- Pad width/length and solder-mask opening
- Layer transition location
- Signal-via stub length
- Ground-via placement
- Back-drilling or blind/buried vias where required
- Intra-pair skew through the entire launch
- Connector orientation relative to routing layers
Use the manufacturer’s reference footprint as the initial model, then adapt it to the actual PCB stack-up.
8. Mechanical variables affect electrical performance
Stack height, contact wipe and manufacturing tolerance can change the electrical path. Ask whether the S-parameter data covers:
- Minimum and maximum mated height
- Allowed float or misalignment
- Temperature and humidity conditioning
- Mating-cycle aging
- Multiple position counts
A mechanically compatible variant may not have the same high-speed qualification.
9. Selection and validation workflow
- Define interface generation, lanes and topology.
- Build the channel-loss and reflection budget.
- Shortlist connectors with relevant S-parameter data.
- Choose signal/ground pin maps that can be routed.
- Import connector models into the channel simulation.
- Optimize PCB launches and vias.
- Review mechanical stack and assembly tolerance.
- Build a test coupon or prototype.
- Measure the channel and run protocol compliance testing where required.
- Freeze the exact connector, footprint and pin map together.
10. What to request from a supplier
- Exact plug and receptacle numbers
- Supported stack height and pin count
- Differential impedance target
- Touchstone files and port map
- Test fixture/de-embedding description
- Recommended footprint and stack-up assumptions
- Maximum characterized frequency or supported application evidence
- Mating-cycle and environmental qualification
- 3D model and PCB keep-outs
- Sample availability and change-control policy
FAQ
Can a 0.5 mm connector automatically support PCIe 5.0?
No. Pitch does not prove performance. Review the exact connector’s S-parameters, launch and channel margin at 32.0 GT/s.
Is PCIe data rate measured in Gbps?
PCIe link signaling is specified in transfers per second (GT/s). Payload throughput is lower and depends on encoding/protocol overhead and lane count.
Are 85 Ω and 100 Ω connectors interchangeable?
Not by default. Use the impedance target and pin/ground arrangement appropriate for the interface, then validate the complete channel.
Can I use a vendor’s advertised “56 Gbps” connector for any 56G link?
No. Signaling method, insertion-loss budget, crosstalk, encoding and compliance topology differ. Compare measured data with your interface requirements.
Request signal-integrity data
Send GSConn the interface, generation, lane count, stack height, PCB stack-up and preferred pin map. Ask for the exact connector Touchstone model, reference footprint and qualification scope before committing to layout.
Sources and further reading
- https://pcisig.com/what-bit-rates-does-pcie-50-specification-support-and-how-does-it-compare-prior-pcie-generations
- https://pcisig.com/pci-express-6.0-specification
- https://www.molex.com/en-us/products/connectors/board-to-board-connectors/slimstack-connectors
Related guides: b2b-mezzanine-connector-guide.md · b2b-data-center-server-backplane.md · b2b-connector-selection-guide.md
Related reading on GSConn
- Wire-to-Board vs Board-to-Board Connectors
- Industrial USB Connector Guide
- IP67 vs IP68 USB Connector
- Stacked USB Connector Guide
- Request a Quote
Engineering references
- Product drawing, datasheet, material declaration and qualification report for the selected connector series
- IPC land-pattern and acceptability guidance applicable to the PCB assembly class
- Project-specific vibration, shock, thermal and electrical requirements